CSC686 is a processor with ADC, parallel processing, completely static, based on MTP as program storage. This processor has eight processing units. It is based on the RISC architecture and has patented (Field Programmable Processor Array field programmable processor array) technology. The execution cycle of most instructions is an instruction cycle, and only a small number of indirectly addressing instructions require two instruction cycles. CSC686 Built-in 4KW MTP program memory and 512-byte data memory, for the eight FPP units working for use. CSC686 Built-in 11-channel 11-bit resolution A / D converter, where one channel is an internal Bandgap reference voltage or 0.25 * VDD. CSC686 Provide an 8 x voltage gain OPA, two common comparators, and four hardware counters. Councounters are two 16-bit counters and two 8-bit counters, respectively. CSC686 Built-in a hardware pulse capture, 12-bit hardware PWM generator and PWM protection module, to provide the best processing solution for the brushless DC controller.